This application claims the benefit of Korean Application No. P2001-65793 filed on Oct. 24, 2001 under 35 USC xc2xa7 119, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a method for fabricating an MDL (Merged DRAM with Logic) semiconductor device, in which silicide is formed selectively on a logic region and a memory region for enhancing the device reliability.
2. Discussion of the Related Art
As a device packing density increases, the MDL type device is born in a form where a memory (DRAM) and a logic circuit are merged into one chip as a previous stage of a system on chip product for meeting different demands of consumers. Recently, because the MDL composite chip has advantages of providing a small sized, high speed device with a low EMI (Electro Magnetic Interference) and with a low power consumption, researches on the development of the MDL composite chip with a memory product and a logic product formed on one chip, are active in many fields. However, an MDL fabrication process itself is complicated and difficult because a process for fabricating the memory product and a process for fabricating the logic circuit need to be taken into consideration at the same time.
A related art method for fabricating an MDL semiconductor device will be explained with reference to the attached drawings. FIGS. 1A-1J illustrate sectional views showing the steps of a related art process for fabricating an MDL semiconductor device, FIGS. 2A-2F illustrate sectional views showing the steps of another related art process for fabricating an MDL semiconductor device, and FIGS. 3A-3E illustrate sectional views showing the steps of still another related art process for fabricating an MDL semiconductor device.
In general, in the related art MDL semiconductor device, a logic part is required to have high performance while a memory part is required to have reliability. To satisfy these requirements, a gate oxide film with different thicknesses is applied to each of the logic region and the memory region of the device, and a dual poly structure is employed in a transistor in the logic region. In the logic region, for improving device packing density and performance, salicide structures are employed in a gate surface and active surface. In the memory region, for improving the reliability and refresh characteristics, a diffusion active region is employed.
In order to simplify the fabrication process in the related art MDL semiconductor device, either a polycide gate structure (FIGS. 2A-2F) or a salicide gate structure (FIGS. 3A-3E) is employed for forming identical gate structures in the memory region and the logic region. Alternatively, taking characteristics of each region into consideration, a polycide structure is employed in the memory region and the polycide region is removed from the logic region to form a gate according to the fabrication steps shown in FIGS. 1A-1J.
The steps of a related art process for fabricating the MDL semiconductor device will now be explained in more detail referring to FIGS. 1A-1J.
At first, referring to FIG. 1A, a device isolation layer 3 is formed in a semiconductor substrate 26 (or a well region (not shown)) having a logic region 1 and a memory region 2 divided by a boundary line B. In this instance, if an NMOS transistor formation region is taken into consideration, doping concentration in the logic region 1 and the memory region 2 may differ. That is, for improving cell refresh characteristics of the memory region 2, the doping concentration of the memory region 2 may be made relatively low. Then, a first gate oxide film 4 with a first thickness and a first gate forming material layer 5 are formed on the entire surface of the substrate 26 in succession. The first gate forming material layer 5 is formed of undoped polysilicon. Then, a first capping layer 6 of oxide or nitride is formed on the first gate forming material layer 5 for preventing etch damage to the gate layer during the gate etching process.
Referring to FIG. 1B, a photoresist layer is formed on the entire surface of the substrate and patterned selectively for forming a first photoresist pattern layer 7 in the logic region 1 and not in the memory region 2. The exposed first capping layer 6, first gate forming material layer 5, and first gate oxide film 4 are etched selectively by using the first photoresist pattern layer 7 as a mask so that no layer remains above the memory region 2 of the substrate 26. Thereafter, the first photoresist pattern layer 7 is removed.
Referring to FIG. 1C, a second gate oxide film 8 with a second thickness thicker than the first thickness of the first gate oxide film 4, a second gate forming material layer 9 for forming a memory, a tungsten silicide layer 10 and second capping layers 11 and 12 are formed in succession on the entire surface of the resultant structure. In this instance, a polycide structure is used to improve the reliability of the memory and a capacitor forming process to be applied later. The second capping layers 11 and 12 are a stack of an oxide film (11) and a nitride film (12).
Referring to FIG. 1D, photoresist is applied on the entire surface of the resultant structure, and patterned selectively to form a second photoresist pattern layer 13 for patterning a wordline in the memory region 2. A stack of the layers 8, 9, 10, 11, and 12 in the memory region 2 is etched selectively by using the second photoresist pattern layer 13 as a mask, to form gates 14 of a DRAM cell. Thereafter, the second photoresist pattern layer 13 is removed.
Referring to FIG. 1E, source/drain regions 15 are formed in surfaces of the substrate 26 in the exposed memory region 2 by using the gates 14 as a mask. Then, a sidewall spacer forming layer made of oxide or oxide/nitride is formed on the entire resultant structure and etched back to form DRAM sidewall spacers 16 at the sides of each gate 14 of a DRAM cell to form a storage node contact by SAC (Self-Aligned-Contact) in the following process. At the same time, a sidewall spacer is formed at the side of the stack of layers 4-6 and 8-12 in the logic region 1. Then, a material such as BPSG (Boron-Phosphorus-Silicate-Glass), PSG (Phosphorus-Silicate-Glass), HDP (High Density Plasma), or SOG (Spin On Glass) is deposited on the entire surface of the resultant structure to form a gap filling material layer 17 filling the gaps in the memory region 2 and the logic region 1.
Referring to FIG. 1F, the gap filling material layer 17 is planarized by CMP (Chemical Mechanical Polishing) to form a DRAM gate gap filling layer 17a. 
Referring to FIG. 1G, photoresist is coated on the entire surface of the resultant structure, and patterned to leave the photoresist only in the memory region 2 as a third photoresist pattern layer 18. Then, material layers 6, 8, 9, 10, 11, and 12 for forming a DRAM, which remained in the logic region 1, are removed by using the third photoresist pattern layer 18 as a mask to expose the first gate forming material layer 5 in the logic region 1. In this instance, there remains a residual layer 19 at an interface between the logic region 1 and the memory region 2. Thereafter, the third photoresist pattern layer 18 is removed.
Referring to FIG. 1H, photoresist is coated on the entire surface of the resultant structure, and patterned selectively to form a fourth photoresist pattern layer 20 on the first gate forming material layer 5 in the logic region 1 for forming a logic gate. Then, the first gate oxide film 4 and the first gate forming material layer 5, both in the logic region 1, are selectively etched by using the fourth photoresist pattern layer 20 as a mask, to form logic gates 21. The fourth photoresist pattern layer 20 is removed.
Referring to FIG. 1I, impurities are lightly doped into surfaces of the substrate 26 in the exposed logic region 1 to form LDD (Lightly Doped Drain) regions 23. Logic sidewall spacers 22 are formed at the sides of the logic gates 21. Then, impurities are heavily doped by using the logic gates 21 having the logic sidewall spacers 22, to form source/drain 24 of the logic device elements. As shown in the drawings, a high concentration junction may not be formed in the memory region 2.
Referring to FIG. 1J, a metal layer of Ti, Co, or Ni is formed on the entire surface of the resultant structure for forming a silicide layer in the logic region 1. This metal layer subjected to silicidation to form a silicide layer 25 on surfaces of each logic gate 21 and source/drain 24 in the logic region 1. Then, portions of the metal layer that made no reaction in the silicidation are removed, and an annealing is conducted to moderate damages given in the silicidation. Then, though not shown, the logic region 1 and the memory region 2 are planarized, and a cell capacitor is formed in the memory region 2 to complete the fabrication of an MDL semiconductor device.
Another related art process for fabricating an MDL semiconductor device will be explained below referring to FIGS. 2A-2F.
As shown in FIG. 2A, a device isolation layer 33 is formed in a semiconductor substrate 30 (or well region (not shown)) having a logic region 31 and a memory region 32. In this instance, if an NMOS transistor fabrication region is taken into account, doping concentration in the well regions of the logic region 31 and the memory region 32 may differ. That is, in order to enhance cell refresh characteristics of the memory region 32, doping concentration is made relatively lighter. Then, a first gate oxide film 34 with a first thickness is formed on the entire surface of the substrate 30, and photoresist is coated on the entire surface of the first gate oxide film 34. The photoresist is then selectively patterned to leave the photoresist only in the memory region 32, to form a first photoresist pattern layer 35. The first gate oxide film 34 on the exposed logic region 31 of the substrate 30 is removed by using the first photoresist pattern layer 35. Then, a second gate oxide film 36 with a second thickness thinner than the first thickness of the first gate oxide film 34 is formed on a surface of the substrate 30 in the logic region 31.
Referring to FIG. 2B, the first photoresist pattern layer 35 is removed from the memory region 32. A gate forming material layer 37 is deposited on the entire surfaces of the logic region 31 and the memory region 32 having the first and second gate oxide films 34 and 36 formed therein to a thickness required for the memory region 32. A tungsten silicide layer 38, a cap oxide film 39, and a cap nitride layer 40 are then formed in succession over the resultant structure.
Referring to FIG. 2C, photoresist is coated on the entire surface of the resultant structure, and a second photoresist pattern layer 41 is formed for gate patterning, taking a gate line width in the memory region 32 into account. In this instance, the photoresist in the logic region 31 will be patterned to have a gate line width the same as that of the memory region 32. Then, the gate forming material layer 37, the tungsten silicide layer 38, the cap oxide film 39, and the cap nitride layer 40 are selectively etched by using the second photoresist pattern layer 41, to form gate electrodes 42 in the memory region 32 and gate electrodes 43 in the logic region 31. Thereafter, the second photoresist pattern layer 41 is removed.
Referring to FIG. 2D, impurities are lightly doped into surfaces of an exposed substrate by using the gate electrodes 42 and 43 as masks, to form LDD regions 44 both in the memory region 32 and the logic region 31. Then, a sidewall forming material layer is formed on the entire surface of the resultant structure, and is subjected to anisotropic etching to form gate sidewalls 45 on the sides of each gate electrode 42 and 43. Impurities are then heavily doped therein to form source/drain regions 46. In this instance, as shown in the drawings, a high concentration junction may not be formed in the memory region 32, taking the cell leakage characteristics into account.
Referring to FIG. 2E, a silicide blocking layer 47 may be formed on the entire resultant surface, and then photoresist is coated on the entire resultant surface. Then, the photoresist is patterned selectively to form a third photoresist pattern layer 48 only in the memory region 32 and not in the logic region 31. The exposed silicide blocking layer 47 in the logic region 31 is selectively etched by using the third photoresist pattern layer 48 as a mask.
Referring to FIG. 2F, a metal layer is deposited on the entire surface of the resultant structure for forming a silicide layer. This metal layer subjected to silicidation to form a silicide layer 49 on surfaces of the source/drain regions 46 in the logic region 31. An annealing is conducted on the resultant structure to moderate damages to the silicide layer 49 in the silicidation process. Then, though not shown, the logic region 31 and the memory region 32 are planarized, and a cell capacitor is formed in the memory region 32 to complete the fabrication of an MDL semiconductor device.
Another related art process for fabricating an MDL semiconductor device will be explained referring to FIGS. 3A-3E.
As shown in FIG. 3A, a device isolation layer 53 is formed in a semiconductor substrate 50 (or well region (not shown)) having a logic region 51 and a memory region 52. In this instance, if an NMOS transistor fabrication region is taken into account, doping concentration in the well regions of the logic region 51 and the memory region 52 may differ. That is, in order to enhance cell refresh characteristics of the memory region 52, doping concentration is made relatively lighter. Then, a first gate oxide film 54 with a first thickness is formed on the entire surface of the substrate 50, and then photoresist is coated on the first gate oxide film 54. The photoresist is selectively patterned to leave the photoresist only in the memory region 52, thereby forming a first photoresist pattern layer 55 in the memory region 52. The first gate oxide film 54 on the exposed logic region 51 is then removed by using the first photoresist pattern layer 55 as a mask. Then, a second gate oxide film 56 with a second thickness thinner than the first thickness of the first gate oxide film 54 is formed on a surface of the substrate 50 in the logic region 51 and the photoresist 55 is removed.
Referring to FIG. 3B, a gate forming material layer 57 is deposited on the entire surfaces of the logic region 51 and the memory region 52 having the first and second gate films 54 and 56 formed therein. The foregoing process progresses centered on the logic region 51 in which the following step is carried out without formation of a capping layer.
Referring to FIG. 3C, photoresist is coated on the entire surface of the resultant structure, and a second photoresist pattern layer 58 is formed for gate patterning, taking a gate line width in the memory region 52 into account. In this instance, the photoresist in the logic region 51 is also patterned to have a gate line width the same as the memory region 52. Then, the exposed gate forming material layer 57 is selectively etched by using the second photoresist pattern layer 58, to form gate electrodes 59 in the memory region 52 and gate electrodes 60 in the logic region 51. The second photoresist pattern layer 58 is removed.
Referring to FIG. 3D, impurities are lightly doped into surfaces of the exposed substrate 50 by using the gate electrodes 59 and 60 as masks, to form LDD regions 61 both in the memory region 52 and the logic region 51. Then, a sidewall forming material layer is formed on the entire surface of the resultant structure, which is subjected to anisotropic etching to form gate sidewalls 62 at the sides of each gate electrode 59 and 60. Impurities are then heavily doped therein to form source/drain regions 63 in the substrate 50. In this instance, as shown in the drawings, a high concentration junction may not be formed in the memory region 52 taking cell leakage characteristics into account.
Referring to FIG. 3E, silicon layers are formed on the exposed active regions and top surfaces of the gate electrodes 59 and 60 in the logic region 51 and the memory region 52 by SEG (Selective Epitaxial Growth). Then, a refractory metal layer of, such as Ti, Co, or Ni, is sputtered or chemical vapor deposited on the entire resultant surface. Heat is applied to cause reaction between the silicon layer grown by the SEG and the refractory metal layer to form a silicide layer 64.
The aforementioned related art methods for fabricating an MDL semiconductor device have the following problems.
First, in the process of FIGS. 1A-1J in which polycide structure gates are employed in the memory region and non polycide gates are employed in the logic region, although performance improvement in the logic region and stable operation characteristics in the memory region can be obtained, the fabrication process is complicated and increases a production cost. The difficulty of gate etching in the logic region may deteriorate reproducibility of the fabrication process.
Second, the employment of polycide gate structures both in the memory region and the logic region in the fabrication process shown in FIGS. 2A-2F increases a gate resistance in the logic region. The employment of polycide gate structures both in the memory region and the logic region causes difficulty in formation of a dual gate N+/P+. And, even if the dual gate is formed, a threshold voltage of P+ gate is unstable due to a thermal budget of P+ ions with highly diffusive characteristics. These factors render the overall performance of the logic region poor, and the device susceptible to failure.
Third, the use of SEG in the process of FIGS. 3A-3E in which the gate has a silicide structure makes securing a uniform resistance performance difficult. Particularly, the application of a silicide contact at the storage node in the memory region causes a great variation of the contact resistance at the contact, and thereby increases a leakage current at the storage node which deteriorates a cell refresh characteristic and device yield, significantly.
Fourth, due to the above problems, the related art methods for fabricating an MDL semiconductor device has a poor applicability because the methods are not applicable to formation of a high performance SOC (System On Chip). Moreover, when a gap filling process of memory cells is carried out after the source/drains are formed, the high temperature thermal process that is subsequently needed deteriorates a PMOS transistor in the logic part.
Accordingly, the present invention is directed to a method for fabricating an MDL semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating an MDL semiconductor device, in which a silicide process is applicable to a logic region and a memory region selectively without a mask, for thereby enhancing a reliability.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating an MDL semiconductor device includes the steps of (a) providing a substrate having a first region and a second region adjoining the first region, (b) forming a first gate forming material layer in the first region, (c) forming a second gate forming material layer in the first region having the first gate forming material layer formed therein and the second region, (d) selectively patterning the second gate forming material layer to form second gates in the second region and a boundary dummy pattern layer at a boundary of the first and second regions, and (e) selectively patterning the first gate forming material layer to form first gates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.